The demand for reduced size and increased complexity of electronic components has driven the industry to produce smaller and more complex integrated circuits. These same trends have forced the development of microelectronic packages having smaller footprints, higher lead counts, and better electrical and thermal performance. Ball grid arrays (BGA) were developed in part to meet the demand for microelectronic packages having higher lead counts and smaller footprints.
FIG. 1 is a cross sectional view of an example of a BGA microelectronic package, which commonly consists of microelectronic die 14 electrically interconnected with a carrier substrate 12, and one or more other elements, such as electrical interconnects, a die lid, a heat dissipation device, among others (not shown). Carrier substrate 12 contains an array of substrate interconnects 18 that have electrically conductive interconnect material 22 coupled thereon. Interconnect material 22 is typically a solder, but can be any reflowable electrically conductive material. Substrate interconnects 18 are configured into an array to electrically interconnect with a corresponding array of system substrate interconnects 20 of a system substrate 16. An example of a system substrate 16 is a printed circuit board (PCB), which, in some applications, is referred to as a motherboard.
Conventionally, a dielectric material 24 is used as a means for defining electrical interconnects 18 or 20 and for the implantation of interconnect material 22 on the substrate interconnects 18. Though not shown, interconnect material 22 can be coupled to system substrate interconnects 20. The dielectric material, also known as solder mask or solder resist, functions to prevent the interconnect material 22 from migrating to areas where it is not desired, prevents bridging and defines the contact pad surface for which the interconnect material 22 is deposited for electrical interconnection with a substrate. Defining the substrate interconnect in this manner is known as a dielectric defined interconnect, or solder mask defined interconnect.
FIG. 2A is a top view of a dielectric defined interconnect. Dielectric 24 covers a conductive trace 26 and the outer edge of substrate interconnect 18, thereby defining an exposed interconnect portion 28 upon which interconnect material 22 (not shown) is coupled. FIG. 2B is a cross sectional view of a dielectric defined interconnect taken along the line 2B-2B of FIG. 2A. Dielectric 24 creates an opening to the exposed interconnect portion 28, upon which the interconnect material 22 is deposited. The dielectric defined edge 30 creates a stress concentration point, which can initiate cracking or cause fatigue in the electrical interconnection. There is a propensity for the electrical interconnection between the system substrate 16 and the carrier substrate 12 at a point below the die 14 to fatigue or crack before electrical interconnections outside the die perimeter. This propensity for crack initiation is on both the microelectronic package side and the system substrate side, and is due to the coefficient of thermal expansion (CTE) mismatch between the die 14 and carrier substrate 12 during temperature cycling.
Another microelectronic package interconnect design for BGAs is known in the art as a non-dielectric defined interconnect or non-solder mask defined interconnect. An example of a non-dielectric defined interconnect 32 is shown in FIGS. 3A and 3B. As seen in FIG. 3A, the dielectric 24 does not define the interconnect edge 31, but is a slight distance away at 33, which results in the metal of the substrate defining the interconnect edge of a non-dielectric defined interconnect 32.
FIG. 3B is a cross section of FIG. 3A. As shown, the non-dielectric defined interconnect 32 typically results in a stronger electrical interconnection that is less susceptible to fatigue or cracking because there is no dielectric edge (30 in FIG. 2B with respect to a dielectric defined interconnect) engaging the electrical interconnection, which may prevent a stress concentration point. The non-dielectric defined interconnect has drawbacks, however, such as, higher manufacturing costs and higher bridging potential compared to a dielectric defined interconnect.
Several failure patterns are observed in dielectric defined electrical interconnects, particularly those under or directly opposite the die 14 (see FIG. 1). First the dielectric defined interconnect size to system substrate interconnect size ratio can dictate where cracks initiate (i.e. on the system substrate side or the microelectronic package side). Where the ratio is small the electrical interconnection failure tends to be on the microelectronic package side of the electrical interconnection; whereas for larger ratios, the failure tends to be at the system substrate side of the electrical interconnection. This failure has been reduced by optimizing the dielectric opening to interconnect size ratio, which previously was not a critical parameter.
A second failure pattern in dielectric defined interconnects involves the crack initiation point and crack propagation. FIGS. 4A and 4B show the crack initiation and propagation patterns for failing electrical interconnections on both the system substrate 16 side (system substrate side) and the microelectronic package carrier substrate 12 side (microelectronic package side), respectively. FIG. 4A shows the crack initiation point 34 at the system substrate side as being on the outside edge of the electrical interconnection distal to the center portion 36. Cracking generally propagates from the electrical interconnects farthest from the center portion 36 toward the center portion 36 as shown by inward crack propagation arrows 40. FIG. 4B shows the crack initiation point 34′ being on the inside edge of the electrical interconnection proximal to the center 36′ and the propagation of cracks move outward from the center portion 36′, as shown by outward crack propagation arrows 40′. The opposite crack initiation and propagation pattern between the electrical interconnection on the system substrate level versus the microelectronic package level is due to the shear stress caused by the CTE mismatch.
Accordingly new configurations and methods are needed for providing BGA interconnects that resists the cracking tendencies of the electrical interconnections, including crack initiation and crack propagation.